Design and Hardware-In-The-Loop Simulation of a Virtual Synchronous Generator Associated With Harmonic Supression Methods For a Solid-State Transformer Control


Publication date: 07/11/2023

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Summary: The rapid growing rate of distributed generation (DG), particularly photovoltaic units, reduces the active power share from synchronous generators (SG) in centralized plants. Photovoltaic DG units lack rotational inertia, posing instability risks in high DG penetration scenarios. To address this issue, a proposed solution is to introduce virtual inertia through converter control, creating a virtual synchronous generator (VSG), enabling the enhancement of the stability of the electrical system. In this regard, this work aimed to design and carry out hardware-in-the-loop (HIL) simulations of a VSG to control a
solid-state transformer (SST), as a way of providing virtual inertia to the grid. Additionally, two harmonic supression methods were implemented to maintain power quality when there are nonlinear loads connected to the SST, the first is named impedance reshaping (IR) and the second, linear active disturbance rejection control (LADRC). The control of the converters was embedded in a digital signal processor (DPS) from Texas Instrumets and real-time HIL simulations were carried out with the hardware Typhoon HIL 404 to emulate the system composed by the electrical grid, filters, converters, DG and loads. The SST’s input and output voltage and current signals were transmitted from the Typhoon HIL 404 to the DSP, which processed them and generated the PWMs signals that were transmitted back to the Typhoon HIL 404 to drive the switches of the converters. Transient scenarios such as voltage sag, frequency drop, load variations, and DG power injection were analysed. Results showed that the VSG control with harmonic supression methods effectively provided virtual inertia to the grid at the point of common coupling (PCC) while reducing the total harmonic distortion (THD) of the VSG voltage at the load side. IR method outperformed LADRC in reducing THD compared to the scenario without the use of harmonic supression method, achieving a 50.79% THD reduction when considering all loads connected to the SST and 72.89% when considering only the nonlinear load. LADRC achieved 42.07% and 56.13% THD reductions respectively. However, LADRC provided greater stability of the SST’s output voltage during voltage sag with smaller variations (−0.31% to 0.39%) compared to IR method (−3.15% to 2.36%), resulting in smaller power variations. The same result was observed for the frequency dip in the grid
voltage connected to the SST, WHERE the output voltage had negligible variations with the LADRC method, WHEREas variations ranged between −3.94% and 5.51% with the IR method. In these scenarios, the LADRC method also demonstrated smaller variations in the output voltage frequency and lower values for the RMS input current of the SST.
Keywords: Distributed generation; Solid-state transformer; Virtual Synchronous Generator; Harmonic supression; Hardware-in-the-loop.

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